Architecture and Control of a DFLL for Fine-Grain DVFS in GALS Structures

Fine-grain Dynamic Voltage and Frequency Scaling (DVFS) is becoming a requirement for Globally-Asynchronous Locally-Synchronous (GALS) architectures. However, the area overhead of adding voltage and frequency control engines in each voltage and frequency island must be taken into account to optimize the circuit. A small-area fast-reprogrammable Digital Frequency-Locked Loop (DFLL) engine is a suited option, since its implementation in 32nm represents 0.0016 mm2, being 4 to 20 times smaller than classical used techniques such as Phase-Locked Loop (PLL) in the same technology. Another relevant aspect with respect to the DFLL is the control design, which must be suited for low area hardware. In this paper, an analytical model of the system is deduced from accurate Spice simulations. It takes into account the delay introduced by the sensor. From this model, an optimal and robust controller with a minimum implementation area is developed. The closed-loop system stability as well as the robustness against process and temperature variations are also ensured.